Analog to digital conversion is widely used in applications involving numerous sensors, such as automotive applications. In some conventional forms of analog to digital conversion, an analog source (such as a sensor) provides an input charge to a sampling capacitor, and the charge accumulated, hence the voltage sampled on the sampling capacitor over a sampling period is converted to a digital value.
It is desired to reduce the input charge so that voltage drop across an input filter of the analog to digital converter is reduced, enabling an increase in sampling rate. Existing technology accomplishes this goal using rail to rail buffers to sample the input voltage. While this eliminates the concern about input charge, such buffers consume a large amount of on-chip area and have high power consumption, particularly with a high sampling rate. Particularly for cases where there are numerous analog input sources, the use of such buffers becomes too costly in terms of area and power consumption.
Therefore, further development in this area is needed.